Future Compute Infrastructure and Post-Quantum Security
The true bottleneck for AI infrastructure in the 2026-2035 period lies in memory bandwidth and power consumption, not chip speed, while rapid advancements in quantum algorithms necessitate an immediate global migration to post-quantum cryptography.
Future Compute Infrastructure and Post-Quantum Security
Executive Summary
The 2026-2035 period presents two parallel challenges for global digital infrastructure. First, the explosion of generative AI is pushing data centers to their physical limits: the bottleneck is no longer operations per second (FLOPS) but rather memory bandwidth and power consumption. Second, rapid advancements in quantum algorithms are narrowing the window for a quantum computer capable of breaking RSA-2048 (“Q-Day”) to 2030-2035, necessitating an immediate global migration to Post-Quantum Cryptography (PQC).
Key points, clearly distinguishing between production, lab, roadmap, and hype:
- The memory wall is real. HBM4, with its 2048-bit interface, entered mass production in February 2026 (Samsung, SK Hynix, Micron). This is production, no longer a roadmap item.
- The power crisis is real. Data centers consumed approximately 415 TWh in 2024 (~1.5% of global electricity), and the IEA forecasts consumption could exceed 1,000 TWh by 2026, progressing towards ~945 TWh in the baseline scenario for 2030.
- PQC is now an official standard. NIST issued FIPS 203, 204, and 205 in August 2024. The NIST IR 8547 roadmap sets milestones to deprecate RSA-2048 by 2030 and completely disallow it by 2035.
- Q-Day is closer due to algorithms, not just hardware. A paper by Craig Gidney (Google, May 2025) reduced the estimated cost of breaking RSA-2048 to under 1 million physical qubits running for approximately one week — a 20-fold reduction from the previous estimate of 20 million qubits.
- Optical and neuromorphic computing remain in the lab/niche stage. Do not mistake them for near-future GPU replacements.
Scaling Limits and the Energy Crisis
The Memory Wall: The Decade’s True Bottleneck
Moore’s Law isn’t “dead” but its focus has shifted. Scaling transistors below 2nm no longer yields linear performance gains for the economic cost, leading the industry to pivot towards advanced packaging: CoWoS, 3D stacking, and chiplet architectures. In the AI context, performance growth is no longer dependent on single-core power but is instead constrained by the “memory wall” — GPUs must wait for data to be loaded quickly enough.
HBM4 is the direct answer to this bottleneck. Unlike the incremental upgrades of HBM3E, HBM4 doubles the interface width to 2048-bit with 32 independent channels, achieving over 2.0 TB/s per stack (up to 3.3 TB/s in high-end configurations). SK Hynix has demonstrated a 16-layer stack with 48 GB capacity; Micron offers a 12-layer stack with 36 GB. Mass production commenced in February 2026, and the HBM market is projected to grow by up to 58% in 2026.
However, stacking up to 16 DRAM layers creates real barriers regarding heat and wafer yield. This is why liquid cooling is transitioning from an option to a necessity for high-density racks.
The Power Problem
The most reliable figures come from the IEA: data centers consumed approximately 415 TWh in 2024, equivalent to ~1.5% of global electricity. Given the trend of “power-hungry” GPU investments, the IEA forecasts total consumption could exceed 1,000 TWh by 2026 — roughly equivalent to Japan’s entire electricity consumption — and reach approximately 945 TWh by 2030 in the baseline scenario (nearly 3% of global electricity), progressing towards ~1,200 TWh by 2035.
The practical consequence: national power grids are becoming a hard constraint on AI expansion. Operators are pushing for liquid cooling to increase electrical efficiency and betting on stable power sources — including small modular nuclear reactors (SMRs) and long-term renewable power purchase agreements. It’s important to note: commercial-scale SMRs are still a roadmap item, not yet in production for most markets; this is a long-term bet, not a ready solution for 2026-2027.
Emerging Hardware Trends
It’s crucial to distinguish the maturity level of each trend to avoid incorrect expectations.
Optical Interconnect — Closest to Production
Optical interconnects (optical/co-packaged optics, CPO) represent the trend closest to production for addressing data transfer bottlenecks between rack clusters and chip-to-chip. Intel has demonstrated its Optical Compute Interconnect (OCI) chiplet co-packaged with a prototype CPU, supporting 4 Tbps bidirectional speeds with a roadmap to tens of Tbps per device; over 5 million silicon photonics transceivers have already been deployed in hyperscale data centers. Nevertheless, debates persist regarding cost compared to optimizing next-generation copper cables for short distances.
Photonic Computing — Still in the Lab
Photonic computing (performing computations using light instead of electrons) has the potential for significantly lower energy consumption than CMOS, but it remains at the lab/research stage. Integrating optics into large-scale chip manufacturing, ensuring thermal stability, and programmability for general AI workloads still lack commercial solutions before 2030. The question of “whether photonics will completely replace von Neumann architecture by 2035” currently belongs to basic research, not deployment plans.
Neuromorphic Computing — Niche Market
Neuromorphic computing (such as Intel’s Loihi chip, using spiking neural networks) is efficient for certain specialized edge inference tasks with ultra-low power consumption. However, it cannot yet replace GPUs in AI training due to a lack of software ecosystem. This is a niche market, not a direct competitor to cloud GPUs in this decade.
Chiplets & 3D Stacking — Already in Production
In contrast, chiplets and 3D packaging are already in production and serve as the practical pillars sustaining progress as transistor scaling slows. This is where short-term engineering value lies, not in photonics.
Post-Quantum Security and Timeline
Standards Finalized
NIST has finalized three PQC standards, effective August 14, 2024:
- FIPS 203 — ML-KEM (based on CRYSTALS-Kyber): key-establishment mechanism, three levels ML-KEM-512/768/1024.
- FIPS 204 — ML-DSA (based on CRYSTALS-Dilithium): digital signature algorithm based on algebraic lattices.
- FIPS 205 — SLH-DSA (SPHINCS+): hash-based digital signature algorithm, serving as a mathematically independent backup option to the two lattice-based standards above.
This marks a “production” milestone: enterprises can deploy immediately, no need to wait.
”Harvest Now, Decrypt Later” — A Real Risk
The most urgent threat does not require Q-Day to occur for consequences to manifest. In the “Harvest Now, Decrypt Later” (HNDL) scenario, adversaries collect and store RSA/ECC encrypted data today to decrypt it once a quantum computer becomes available. Data with a “secret lifetime” exceeding 10 years — state secrets, medical records, financial data, intellectual property — is at the highest risk right now, as their required confidentiality period extends beyond the forecasted Q-Day window.
Timeline for Deprecating Classical Cryptography
The NIST IR 8547 roadmap (public release 11/2024) and NSA CNSA 2.0 set clear milestones:
- By 2030 — Deprecate: RSA-2048 and ECC P-256 (112-bit security level) are categorized as deprecated, no longer suitable for new deployments. Networking/equipment must transition to CNSA 2.0.
- 2031-2033 — CNSA 2.0 Mandated: extended to software, operating systems, cloud services.
- By 2035 — Disallow: all remaining uses of RSA/ECC (including RSA-3072 or P-384) are prohibited under NIST standards; all national security systems must be quantum-resistant.
Q-Day: Forecasts and Debates
The most significant breakthrough in 2025 came from algorithms, not hardware. A paper by Craig Gidney (Google, May 2025) demonstrated that only approximately 1,000-1,400 logical qubits running for about one week would be needed to factor RSA-2048 — leading to an estimate of under 1 million physical qubits, a roughly 20-fold reduction compared to the previous 20 million figure, thanks to over a 100-fold reduction in Toffoli gates. Coupled with new architectures (neutral-atom) and QLDPC error correction codes, the 2030 milestone is no longer “impossible.”
Expert consensus currently places the Q-Day window between 2030-2035, with some earlier estimates (2029-2030) and some later ones (up to 2034-2044). It’s important to acknowledge dissenting opinions: some argue that the Q-Day risk is exaggerated to boost security hardware sales. However, the reduced qubit estimate is a peer-reviewed research finding, and the mainstream view (NIST, NSA, Google) considers the risk to be real and present — thus, the sensible defensive action is early migration, regardless of whether Q-Day falls at the beginning or end of the window.
The Real Bottlenecks
Setting aside the hype, the three real bottlenecks for the 2026-2035 period are:
- Memory bandwidth and power consumption, not FLOPS. AI doesn’t lack compute power; it lacks data loaded quickly enough, cheaply enough, and cool enough. HBM4 and liquid cooling address the technical aspects; grid power is the economic-political constraint.
- PQC migration is an operational problem, not a mathematical one. The math is done (FIPS 203/204/205). The difficulty lies in inventorying all uses of cryptography in legacy systems and replacing them before 2030 without service disruption.
- Misplaced expectations for new hardware. Photonic computing and neuromorphic are long-term research; betting on them as short-term GPU replacements is a mistake. Real short-term value lies in chiplets, 3D stacking, and optical interconnects.
Practical Recommendations
- Create a Cryptographic Bill of Materials (CBOM): identify all instances of RSA/ECC usage and the “secret lifetime” of each data type. Data requiring confidentiality for over 10 years must be prioritized.
- Implement PQC in Hybrid Mode starting in 2026: run classical and PQC algorithms in parallel to maintain stability while the PQC ecosystem matures. Waiting for a “more optimal” standard is a strategic mistake — the standard is already here.
- Treat power as an architectural constraint: prioritize infrastructure capable of integrating liquid cooling and stable power sources; view SMRs as a long-term bet, not a ready-to-deploy solution.
References
- IEA — Energy demand from AI: https://www.iea.org/reports/energy-and-ai/energy-demand-from-ai
- NIST — FIPS 203 (ML-KEM) final: https://csrc.nist.gov/pubs/fips/203/final
- NIST — Releases First 3 Finalized PQC Standards (8/2024): https://www.nist.gov/news-events/news/2024/08/nist-releases-first-3-finalized-post-quantum-encryption-standards
- NIST IR 8547 (public release) — Transition to PQC: https://nvlpubs.nist.gov/nistpubs/ir/2024/NIST.IR.8547.ipd.pdf
- PostQuantum — Quantum Breakthrough Slashes Qubit Needs for RSA-2048 (Gidney 5/2025): https://postquantum.com/quantum-research/quantum-breakthrough-rsa-2048/
- Tom’s Hardware — HBM roadmaps (Micron, Samsung, SK Hynix): https://www.tomshardware.com/tech-industry/semiconductors/hbm-roadmaps-for-micron-samsung-and-sk-hynix-to-hbm4-and-beyond
- Intel — Silicon Photonics / Optical Compute Interconnect: https://www.intel.com/content/www/us/en/products/details/network-io/silicon-photonics.html
- Data Center Frontier — IEA sees data center energy doubling by 2026: https://www.datacenterfrontier.com/energy/article/33038469/iea-study-sees-ai-cryptocurrency-doubling-data-center-energy-consumption-by-2026
Research source: research-output R012 (Gemini), verified and expanded. Updated: 2026-06-13.